1. Field of the Invention
The present invention relates to a semiconductor device in which a gate electrode is formed on a semiconductor substrate and a method for manufacturing the same, and is preferable to be applied to a fine semiconductor device having high aspect ratio of an area between the gate electrodes and in which a gate length is shortened.
2. Description of the Related Art
Recently, a finer semiconductor device with higher-density design is increasingly demanded and the gate length and the distance between gate electrodes are being further shortened in a DRAM and logic combined type device or a logic device. As a result, it is difficult to obtain excellent ability of filling the area between the gate electrodes when an ordinary silicon oxide film is used as an interlayer insulating film, and a BPSG (Boro-Phospho Silicate Glass) film or a USG (HDP-USG: High Density Plasma-CVD—Undoped Silicate Glass) film by a high-density plasma CVD method are becoming used alternatively.
The BPSG film covers the gate electrode and has a characteristic that it has a high etching selection ratio with a silicon nitride film, which works as an etching stopper in forming a contact hole. If this BPSG film is used as the interlayer insulating film, it is possible to sufficiently respond to a SAC (Self Align Contact) technique applied according to the shortened gate length and distance between the gate electrodes.
In filling the shortened area between the gate electrodes with the BPSG film, a so-called slit void occurs at the film-formation. If a contact hole is formed between the gate electrodes, adjacent contact holes make a short circuit due to the slit void, and therefore it is necessary to eliminate the slit void by melting, reflowing, and annealing the BPSG film.
In the semiconductor device with the shortened area between the gate electrodes, if thermal treatment at the high temperature is performed in a manufacturing process thereof, an impurity doped to the semiconductor substrate diffuses up to a gate insulating film in forming a source/drain, which results in characteristic change in a threshold voltage. Further, due to the thermal treatment at the high temperature, an impurity introduced to lower the resistance of the gate electrode, which consists of polycrystalline silicon, boron (B) for example, penetrates the gate insulating film and diffuses to the source/drain (so-called boron penetration). In order to avoid these disadvantages, it is essential to control the treatment temperature of the manufacturing process at 650° C. or lower. However, an at least 700° C. and usually 800° C. or higher temperature condition is required in the melting, reflowing, and annealing step of the BPSG film, and it is impossible to perform melting, reflowing, and annealing because of the above-described demand for controlling the temperature, which brings about a problem that the slit void cannot be removed.
On the other hand, for the HDP-USG film, since a mixed gas of SiH4, O2, and Ar is used as a growth gas in its formation and the melting, reflowing, and annealing step at the high temperature after the film-formation, which is essential for the BPSG film, is not needed, the above-described demand for controlling the temperature is responded. However, there is a problem that it is extremely difficult for the HDP-USG film to respond to the demand for the further finer apparatus, specifically, to secure sufficient filling ability for the semiconductor device in which the aspect ratio of the area between the gate electrodes is 6 or higher.